Access times are important in memory devices, such as first-in first-out (FIFO) buffers, where one device discontinues the driving of a common data output bus as a second device begins the driving of the common data output bus. FIG. 1 illustrates a circuit 10 implementing such a configuration. The circuit 10 generally comprises a first FIFO 12 and a second FIFO 14. The first FIFO 12 has an input 16 that receives an output enable signal OEB and an input 18 that receives a read clock signal RCLK. The second FIFO 14 has an input 20 that receives the output enable signal OEB and an input 22 that receives the read clock signal RCLK. Both the first FIFO 12 and the second FIFO 14 present data to the common data output bus 24. With a standard read data access, the common data output bus 24 quickly responds to either the first FIFO 12 or the second FIFO 14. When two successive read data accesses cross the boundary between the first FIFO 12 and the second FIFO 14, an internal read clock signal and an internal output enable signal generally make a transition between the first FIFO 12 and the second FIFO 14. The output enable signal OEB is active throughout the transition. As a result, there is a longer path from the read clock signal RCLK to the common data output bus 24 during a read data access that crosses the boundary as compared to a normal read data access that does not cross the boundary. As the speed of the FIFOs increases (e.g., in excess of 100 MHz with 8 ns data access times) the problem associated with reads that cross physical device boundaries increases.
FIG. 2 shows the output circuitry 26 contained in each of the first FIFO 12 and the second FIFO 14 shown in FIG. 1. The output circuitry 26 generally comprises an output enable block 28, a read clock block 30, an expansion detection block 32, an output buffer 34, an output driver 36, an output register 37 and an output 38. The output enable block 28 receives the output enable signal OEB at an input 40 and receives a signal from the expansion detection block 32 at an input 42. The output enable block 28 presents a signal to an input 44 of the output buffer 34. The read clock block 30 receives the read clock signal RCLK at an input 46 and presents an output to both an input 47 and an input 49 of output register 37 as well as to an input 48 of the expansion detection block 32. The output buffer 34 presents a signal PU and a signal PD to the output driver 36. The output driver 36 presents an output signal Q at the output 38 that is presented to the common data output bus 24 in FIG. 1.